Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

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Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

Technical Report | 更新时间：2024-06-05

- Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips
- Journal on Communications Vol. 33, Issue 11, Pages: 151-158(2012)
- 作者机构：
  
  1. 北京大学深圳研究生院，广东深圳 518055
  2. 北京大学微处理器研发中心，北京 100871
- 作者简介：
- 基金信息：
  
  The National High Technology Research and Development Program of China(863 Program)(2006AA010202)
- DOI：10.3969/j.issn.1000-436x.2012.11.019
  CLC： TP302
- Online First：2012-11，
  
  Published：25 November 2012
- 稿件说明：
移动端阅览
Dan LIU, Yi FENG, Xiang-lei DANG, et al. Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips[J]. Journal on Communications, 2012, 33(11): 151-158.
DOI：

Dan LIU, Yi FENG, Xiang-lei DANG, et al. Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips[J]. Journal on Communications, 2012, 33(11): 151-158. DOI： 10.3969/j.issn.1000-436x.2012.11.019.

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