Secure interface architecture for the software defined system on wafer

LI Peijie; SHEN Jianliang; GUO Wei; CAO Zhipeng; MEI Bo

doi:10.11959/j.issn.1000-436x.2024190

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Secure interface architecture for the software defined system on wafer

Papers | 更新时间：2024-11-14

- Secure interface architecture for the software defined system on wafer
- Journal on Communications Vol. 45, Issue 10, Pages: 41-54(2024)
- 作者机构：
  
  信息工程大学信息技术研究所，河南郑州 450002
- 作者简介：
- 基金信息：
  
  The National Key Research and Development Program of China(2022YFB4401401)
- DOI：10.11959/j.issn.1000-436x.2024190
  CLC： TP309.2
- Received：23 July 2024，
  
  Revised：2024-09-28，
  
  Published：25 October 2024
- 稿件说明：
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李沛杰,沈剑良,郭威等.面向软件定义晶上系统的安全互连接口架构[J].通信学报,2024,45(10):41-54.

LI Peijie,SHEN Jianliang,GUO Wei,et al.Secure interface architecture for the software defined system on wafer[J].Journal on Communications,2024,45(10):41-54.
李沛杰,沈剑良,郭威等.面向软件定义晶上系统的安全互连接口架构[J].通信学报,2024,45(10):41-54. DOI： 10.11959/j.issn.1000-436x.2024190.

LI Peijie,SHEN Jianliang,GUO Wei,et al.Secure interface architecture for the software defined system on wafer[J].Journal on Communications,2024,45(10):41-54. DOI： 10.11959/j.issn.1000-436x.2024190.

摘要

针对软件定义晶上系统中芯粒互连接口缺乏动态性和异构性导致系统易被恶意芯粒攻击的问题，通过最大限度复用功能逻辑，提出一种动态异构冗余的安全互连接口架构。首先基于软件定义互连技术在电路结构、传输协议和报文结构上进行异构性设计，然后增加裁决调度机制实现威胁定位和动态重构，最后对所提架构进行了晶圆级芯粒流片验证。实验表明，所设计的安全互连接口架构在有限资源开销下具有良好的威胁检测、定位与动态防御效果。

Abstract

To address the lack of dynamic and heterologous characteristics for interconnect interface in software defined system on wafer

a dynamic heterologous redundancy secure interface (DHR-SI) architecture was proposed to maximize the reuse of functional logic. First

based on software defined interconnect technology

the heterogeneous characteristics were implemented in terms of circuit structure

transmission protocol

and message content. And then an arbitration scheduling mechanism was designed to achieve threat localization and dynamic reconfiguration. Finally

the architecture was validated and tested through a wafer scale chiplet. The experimental analysis shows that the proposed DHR-SI architecture has excellent threat detection

localization

and dynamic defense capabilities with limited overhead.

关键词

Keywords

references

吴林晟 , 毛军发 . 从集成电路到集成系统 [J ] . 中国科学: 信息科学 , 2023 , 53 ( 10 ): 1843 - 1857 .

WU L S , MAO J F . From integrated circuits to integrated systems [J ] . Scientia Sinica (Informationis) , 2023 , 53 ( 10 ): 1843 - 1857 .

邬江兴 , 刘勤让 , 沈剑良 , 等 . 从SoC到SDSoW: 微电子发展的新范式 [J ] . 中国科学: 信息科学 , 2024 , 54 ( 6 ): 1350 - 1368 .

WU J X , LIU Q R , SHEN J L , et al . From SoC to SDSoW: a new paradigm for microelectronics development [J ] . Scientia Sinica (Informationis) , 2024 , 54 ( 6 ): 1350 - 1368 .

邬江兴 . 工业控制网络广义功能安全问题与解决之道 [J ] . 信息安全研究 , 2022 , 8 ( 6 ): 524 - 527 .

WU J X . Generalized functional safety problems and solutions in industry control network [J ] . Journal of Information Security Research , 2022 , 8 ( 6 ): 524 - 527 .

邬江兴 . 网络空间内生安全—拟态防御与广义鲁棒控制 [M ] . 北京 : 科学出版社 , 2020 .

WU J X . Principle of cyberspace mimic defense-generalized robust control and endogenous security [M ] . Beijing : Science Press , 2020 .

李沛杰 , 刘勤让 , 陈艇 , 等 . 异构集成互连接口研究综述 [J ] . 集成电路与嵌入式系统 , 2024 , 24 ( 2 ): 31 - 40 .

LI P J , LIU Q R , CHEN T , et al . Research on the heterogeneous integrated interconnect interface [J ] . Integrated Circuits and Embedded Systems , 2024 , 24 ( 2 ): 31 - 40 .

JANGAM S , PAL S , BAJWA A , et al . Latency, bandwidth and power benefits of the SuperCHIPS integration scheme [C ] // Proceedings of the 2017 IEEE 67th Electronic Components and Technology Conference (ECTC) . Piscataway : IEEE Press , 2017 : 86 - 94 .

SHARMA D D , PASDAST G , QIAN Z G , et al . Universal chiplet interconnect express (UCIe): an open industry standard for innovations with chiplets at package level [J ] . IEEE Transactions on Components , Packaging and Manufacturing Technology , 2022 , 12 ( 9 ): 1423 - 1431 .

ARDALAN S , CIRIT H , FARJAD R , et al . Bunch of wires: an open die-to-die interface [C ] // Proceedings of the 2020 IEEE Symposium on High-Performance Interconnects (HOTI) . Piscataway : IEEE Press , 2020 : 9 - 16 .

CHARLES S , MISHRA P . A survey of network-on-chip security attacks and countermeasures [J ] . ACM Computing Surveys , 2022 , 54 ( 5 ): 1 - 36 .

DOFE J , GU P , STOW D , et al . Security threats and countermeasures in three-dimensional integrated circuits [C ] // Proceedings of the Great Lakes Symposium on VLSI 2017 . New York : ACM Press , 2017 : 321 - 326 .

NABEEL M , ASHRAF M , PATNAIK S , et al . 2.5D root of trust: secure system-level integration of untrusted chiplets [J ] . IEEE Transactions on Computers , 2020 , 69 ( 11 ): 1611 - 1625 .

CHARLES S , MISHRA P . Reconfigurable network-on-chip security architecture [J ] . ACM Transactions on Design Automation of Electronic Systems , 2020 , 25 ( 6 ): 1 - 25 .

FACCENDA R F , COMARÚ G , CAIMI L L , et al . A comprehensive framework for systemic security management in NoC-based many-cores [J ] . IEEE Access , 2023 , 11 : 131836 - 131847 .

BORATEN T , KODI A K . Mitigation of denial of service attack with hardware trojans in NoC architectures [C ] // Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS) . Piscataway : IEEE Press , 2016 : 1091 - 1100 .

THEJASWINI P , VIVEKANANDA G , ANU H , et al . Hardware Trojan detection and mitigation in noc using key authentication and obfuscation techniques [J ] . EMITTER International Journal of Engineering Technology , 2022 : 370 - 388 .

FIORIN L , PALERMO G , SILVANO C . A configurable monitoring infrastructure for NoC-based architectures [J ] . IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2014 , 22 ( 11 ): 2438 - 2442 .

SUNDARAM J , GOPAL S , THOMAS T P , et al . A reconfigurable asynchronous SERDES for heterogenous chiplet interconnects [C ] // Proceedings of the 2021 22nd International Symposium on Quality Electronic Design (ISQED) . Piscataway : IEEE Press , 2021 : 542 - 546 .

PAL S , LIU J Y , ALAM I , et al . Designing a 2048-chiplet, 14336-core waferscale processor [C ] // Proceedings of the 2021 58th ACM/IEEE Design Automation Conference (DAC) . Piscataway : IEEE Press , 2021 : 1183 - 1188 .

吕平 , 刘勤让 , 邬江兴 , 等 . 新一代软件定义体系结构 [J ] . 中国科学: 信息科学 , 2018 , 48 ( 3 ): 315 - 328 .

LYU P , LIU Q R , WU J X , et al . New generation software-defined architecture [J ] . Scientia Sinica (Informationis) , 2018 , 48 ( 3 ): 315 - 328 .

李沛杰 , 沈剑良 , 苑红晓 , 等 . 一种应用于软件定义互连系统的多协议SerDes电路 [J ] . 电子学报 , 2021 , 49 ( 4 ): 817 - 823 .

LI P J , SHEN J L , YUAN H X , et al . A multi-protocol SerDes circuit for the applications in software defined interconnection system [J ] . Acta Electronica Sinica , 2021 , 49 ( 4 ): 817 - 823 .

LI P J , SHEN J L , LYU P , et al . Architecture design of protocol controller based on traffic-driven software defined interconnection [J ] . Chinese Journal of Electronics , 2024 , 33 ( 2 ): 362 - 370 .

李晓东 , 沈剑良 , 李沛杰 . 基于博弈论模型的物理层协议自协商机制 [J ] . 现代电子技术 , 2023 , 46 ( 8 ): 84 - 90 .

LI X D , SHEN J L , LI P J . Physical layer protocol auto-negotiation mechanism based on game theoretical model [J ] . Modern Electronics Technique , 2023 , 46 ( 8 ): 84 - 90 .

CHARLES S , MISHRA P . Securing network-on-chip using incremental cryptography [C ] // Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) . Piscataway : IEEE Press , 2020 : 168 - 175 .

BORATEN T , KARANTH KODI A . Packet security with path sensitization for NoCs [C ] // Proceedings of the 2016 Design , Automation & Test in Europe Conference & Exhibition (DATE) . Singapore : Research Publishing Services , 2016 : 1136 - 1139 .

RAPARTI V Y , PASRICHA S . Lightweight mitigation of hardware Trojan attacks in NoC-based manycore computing [C ] // Proceedings of the 2019 56th ACM/IEEE Design Automation Conference (DAC) . Piscataway : IEEE Press , 2019 : 1 - 6 .

SUDUSINGHE C , CHARLES S , MISHRA P . Denial-of-service attack detection using machine learning in network-on-chip architectures [C ] // Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip . New York : ACM Press , 2021 : 35 - 40 .

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