Efficient implementation for BFV fully homomorphic encryption algorithm based on Zynq platform

YANG Yatao; CAO Jingpei; CHEN Liangyu; WANG Wei

doi:10.11959/j.issn.1000-436x.2024160

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Efficient implementation for BFV fully homomorphic encryption algorithm based on Zynq platform

Papers | 更新时间：2024-10-10

- Efficient implementation for BFV fully homomorphic encryption algorithm based on Zynq platform
- Journal on Communications Vol. 45, Issue 9, Pages: 192-205(2024)
- 作者机构：
  
  1.北京电子科技学院电子与通信工程系，北京 100070
  2.西安电子科技大学通信工程学院，陕西西安 710071
- 作者简介：
- 基金信息：
  
  The Fundamental Research Funds for the Central Universities(3282024058;3282024052)
- DOI：10.11959/j.issn.1000-436x.2024160
  CLC： TN92
- Received：10 May 2024，
  
  Revised：2024-08-17，
  
  Published：25 September 2024
- 稿件说明：
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杨亚涛,曹景沛,陈亮宇等.基于Zynq平台的BFV全同态加密算法高效实现[J].通信学报,2024,45(09):192-205.

YANG Yatao,CAO Jingpei,CHEN Liangyu,et al.Efficient implementation for BFV fully homomorphic encryption algorithm based on Zynq platform[J].Journal on Communications,2024,45(09):192-205.
杨亚涛,曹景沛,陈亮宇等.基于Zynq平台的BFV全同态加密算法高效实现[J].通信学报,2024,45(09):192-205. DOI： 10.11959/j.issn.1000-436x.2024160.

YANG Yatao,CAO Jingpei,CHEN Liangyu,et al.Efficient implementation for BFV fully homomorphic encryption algorithm based on Zynq platform[J].Journal on Communications,2024,45(09):192-205. DOI： 10.11959/j.issn.1000-436x.2024160.

摘要

针对BFV全同态加密算法，在Zynq平台上设计了一种高效实现方案。该方案结合负包裹卷积与数论变换（NTT）算法，优化并加速了多项式乘法的过程。同时采用流水线设计思想和并行化硬件电路架构，加速BFV算法的RNS实现。系统采用AXI-DMA传输机制高效地实现了ARM和FPGA之间数据传输。在Zynq UltraScale+MPSoC ZCU102平台上测试，系统在200 MHz时钟频率下，执行一次同态加法的平均耗时为0.024 ms；执行一次同态乘法的平均耗时为5.779 ms，其中包括0.874 ms的密文传输时间。与SEAL库和OpenFHE库的实现相比，所提方案的同态加法实现了4.63倍和6.79倍的效率提升，同态乘法实现了4.43倍和2.95倍的效率提升，这为全同态加密算法的实际工程实现提供了重要参考。

Abstract

An efficient implementation scheme for the BFV fully homomorphic encryption algorithm was proposed on the Zynq platform. This scheme effectively integrated the negative wrapped convolution with the number theoretic transform (NTT) algorithm

optimizing and accelerating the polynomial multiplication process. Furthermore

it adopted a pipeline design and parallel hardware architecture to enhance the RNS implementation of the BFV algorithm. The system efficiently implemented data transmission between the ARM processor and FPGA using the AXI-DMA transfer mechanism. Test results on the Zynq UltraScale+MPSoC ZCU102 platform show that the system performs a homomorphic addition in just 0.024 ms and a homomorphic multiplication in 5.779 ms at a 200 MHz clock frequency

which includes 0.874 ms for ciphertext transmission. Compared to the implementations of the SEAL and OpenFHE libraries

the proposed scheme achieves efficiency improvements of 4.63 and 6.79 times for homomorphic addition

and 4.43 and 2.95 times for homomorphic multiplication

providing an important reference for the practical engineering implementation of fully homomorphic encryption algorithms.

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Keywords

references

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