Efficient implementation scheme of SM4 algorithm based on FPGA

ZHANG Hongke; YUAN Haonan; DING Wenxiu; YAN Zheng; LI Bin; LIANG Dong

doi:10.11959/j.issn.1000-436x.2024053

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Efficient implementation scheme of SM4 algorithm based on FPGA

Papers | 更新时间：2024-06-24

- Efficient implementation scheme of SM4 algorithm based on FPGA
- Journal on Communications Vol. 45, Issue 5, Pages: 140-150(2024)
- 作者机构：
  
  1.西安电子科技大学网络与信息安全学院,陕西西安 710126
  2.中国电子科技集团公司第五十四研究所,河北石家庄 050299
  3.西安电子科技大学空天地一体化综合业务网全国重点实验室,陕西西安 710071
  4.西安电子科技大学杭州研究院,浙江杭州 311200
- 作者简介：
- 基金信息：
  
  The National Natural Science Foundation of China(U23A20300;62072351);The Key Research Project of Shaanxi Natural Science Foundation(2023-JC-ZD-35);The Natural Science Basic Research Plan in Shaanxi Province of China(2023-JC-YB-500)
- DOI：10.11959/j.issn.1000-436x.2024053
  CLC： TN92
- Received：01 November 2023，
  
  Revised：2024-02-03，
  
  Published：30 May 2024
- 稿件说明：
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张宏科,袁浩楠,丁文秀等.基于FPGA的SM4算法高效实现方案[J].通信学报,2024,45(05):140-150.

ZHANG Hongke,YUAN Haonan,DING Wenxiu,et al.Efficient implementation scheme of SM4 algorithm based on FPGA[J].Journal on Communications,2024,45(05):140-150.
张宏科,袁浩楠,丁文秀等.基于FPGA的SM4算法高效实现方案[J].通信学报,2024,45(05):140-150. DOI： 10.11959/j.issn.1000-436x.2024053.

ZHANG Hongke,YUAN Haonan,DING Wenxiu,et al.Efficient implementation scheme of SM4 algorithm based on FPGA[J].Journal on Communications,2024,45(05):140-150. DOI： 10.11959/j.issn.1000-436x.2024053.

摘要

针对SM4算法的FPGA实现方案存在数据处理速度不够高和逻辑资源占用过高的问题，提出了基于现场可编程门阵列（FPGA）的高性能、低资源消耗的SM4算法实现方案。所提方案采用循环密钥扩展与32级流水线加解密相结合的架构，循环密钥扩展的方式降低了逻辑资源消耗，32级流水线加解密的方式提高了数据吞吐率。同时，所提方案采用代数式S盒并通过合并线性运算以及在不可约多项式的合并矩阵中筛选最优矩阵运算的方式进一步减少S盒变换的运算量，从而达到降低逻辑资源占用与提高工程数据吞吐率的目的。测试结果显示，该方案比现有最佳方案在数据吞吐率上提升了43%，且资源占用率降低了10%。

Abstract

To address the inefficient data processing performance and excessive resource utilization issues that field-programmable gate array (FPGA)-based SM4 implementations faced

an implementation scheme that adopted both iteration and pipeline in order to reduce resource consumption and improve throughput was proposed. A combination of cyclic key extension and 32 bit pipeline encryption and decryption architecture was adopted by the proposed scheme. The cyclic key extension reduced logical resource consumption

while the 32 bit pipeline encryption and decryption improved data throughput. Additionally

an algebraic S-box that combined linear operations to select an optimal matrix from those generated by different irreducible polynomials was employed. Resource usage and computation overhead was further minimized

thus achieving an increased engineering frequency. Experimental results demonstrate a 43% throughput improvement and a 10% reduction in resource usage compared to the current best scheme.

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Keywords

references

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