High-speed hardware architecture design and implementation of Ed25519 signature verification algorithm

Yiming XUE; Shurong LIU; Shuheng GUO; Yan LI; Cai’e HU

doi:10.11959/j.issn.1000-436x.2022061

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High-speed hardware architecture design and implementation of Ed25519 signature verification algorithm

Papers | 更新时间：2024-06-05

- High-speed hardware architecture design and implementation of Ed25519 signature verification algorithm
- Journal on Communications Vol. 43, Issue 3, Pages: 101-112(2022)
- 作者机构：
  
  1. 中国农业大学信息与电气工程学院，北京 100083
  2. 中国农业大学理学院，北京 100083
  3. 国网北京市电力公司，北京 100031
- 作者简介：
- 基金信息：
  
  The National Natural Science Foundation of China(61872368);The National Key Research and Development Program of China(2021QY2312)
- DOI：10.11959/j.issn.1000-436x.2022061
  CLC： TN918
- Online First：2022-03，
  
  Published：25 March 2022
- 稿件说明：
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Yiming XUE, Shurong LIU, Shuheng GUO, et al. High-speed hardware architecture design and implementation of Ed25519 signature verification algorithm[J]. Journal on Communications, 2022, 43(3): 101-112.
DOI：

Yiming XUE, Shurong LIU, Shuheng GUO, et al. High-speed hardware architecture design and implementation of Ed25519 signature verification algorithm[J]. Journal on Communications, 2022, 43(3): 101-112. DOI： 10.11959/j.issn.1000-436x.2022061.

摘要

针对区块链等特定场景对验签速度有较高要求的特点，设计了一种高速Ed25519验签算法的硬件架构。提出了基于交错NAF的多点乘算法，通过预计算和查表的方式，有效减少了点加、倍点的次数；采用Karatsuba乘法和快速约简方法实现模乘运算，并设计了不需要模加、模减的点加、倍点操作步骤，有效提升了点加、倍点运算的性能。针对解压过程中耗时的模幂运算，设计了模逆和模乘并行的模幂计算方法，提高了解压运算的性能。整个设计充分考虑了资源的复用，在Zynq-7020平台上实现需要13 695个Slices，在81.61 MHz的时钟频率下，每秒能够完成8 347次验签运算。

Abstract

Aiming at the high performance requirements of signature verification for specific scenarios such as blockchain

a high-speed hardware architecture of Ed25519 was proposed.To reduce the number of calculations for point addition and point double

a multiple point multiplication algorithm based on interleaving NAF was conducted by using pre-computation and lookup tables.The modular multiplication operation was realized by using the Karatsuba multiplication and fast reduction method

and the point addition and point double operation was designed without modular addition and subtraction

which could effectively improve the performance of point addition and point double.Given that modular exponentiation was the most time-consuming operation in the decompression process

a new modular exponentiation approach was developed by parallelizing modular inverse and modular multiplication

and therefore the performance of the de-compression operation could be improved.The proposed architecture fully considers the use of resources and is implemented on the Zynq-7020 FPGA platform with 13 695 slices

achieving 8 347 verifications per second at 81.6 MHz.

关键词

Keywords

references

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