Research on <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub>  <mi>F</mi>  <mrow>   <msup>    <mi>p</mi>    <mn>2</mn>   </msup>   </mrow> </msub></math></inline-formula>-FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture

Zhanpeng JIANG; Mingwei SUN; Hai HUANG; Jiang XU; Zhiwei LIU; Rui BAI; Zhou FANG; Jiaxing QU

doi:10.11959/j.issn.1000-436x.2022040

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Research on

F_{p^{2}}

-FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture

Papers | 更新时间：2024-06-05

- Research on $F_{p^{2}}$ -FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture
- Journal on Communications Vol. 43, Issue 2, Pages: 100-108(2022)
- 作者机构：
  
  1. 哈尔滨理工大学计算机科学与技术学院，黑龙江哈尔滨 150080
  2. 哈尔滨理工大学电气与电子工程学院，黑龙江哈尔滨 150080
  3. 黑龙江省网络空间研究中心，黑龙江哈尔滨 150090
- 作者简介：
- 基金信息：
  
  The National Key Research and Development Program of China(2018YFB2202100);The Special Projects for the Central Government to Guide the Development of Local Science and Technology(ZY20B11);The Natural Science Foundation of Heilongjiang(YQ2019F010);The Fundamental Research Funds for the Central Universities of Heilongjiang Province(2019KYYWF0214)
- DOI：10.11959/j.issn.1000-436x.2022040
  CLC： TN918
- Online First：2022-02，
  
  Published：25 February 2022
- 稿件说明：
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Zhanpeng JIANG, Mingwei SUN, Hai HUANG, et al. Research on $F_{p^{2}}$ -FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture[J]. Journal on Communications, 2022, 43(2): 100-108.
DOI：

Zhanpeng JIANG, Mingwei SUN, Hai HUANG, et al. Research on $F_{p^{2}}$ -FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture[J]. Journal on Communications, 2022, 43(2): 100-108. DOI： 10.11959/j.issn.1000-436x.2022040.

Research on

F_{p^{2}}

-FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture

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摘要

针对双线性对运算效率低的问题，提出了一种面向双线性对的二次扩域细集成操作数扫描（

-FIOS）模乘算法。该算法通过优化二次扩域下(AB+CD)mod P的运算过程，有效降低了模乘中的模约减次数；设计了满足不同应用需求的2种硬件架构及其调度方式以提升算法的计算效率；采用TSMC 55 nm工艺实现了双线性对运算单元。与现有文献相比，所设计的架构在一次模乘时间、时钟频率和面积时间积等性能指标上优于同类模乘设计，在整体Optimal ate对运算实现上也有一定的优势。

Abstract

A quadratic extended-domain finely integrated operand scanning (

-FIOS) modular multiplication algorithm for bilinear pairs was proposed to address the problem of low efficiency of bilinear pair operations.The algorithm effectively reduced the number of modular reductions in modular multiplication by optimizing the operation process of (AB+CD)mod P under the quadratic expansion domain.Two hardware architectures and their scheduling methods were designed to meet different application requirements.In order to improve the computational efficiency of the algorithm

the TSMC 55 nm process was used to realize the bilinear pairing operation unit.Compared with the existing literature

the designed architecture is superior to similar modular multiplication designs in performance indicators such as the first modular multiplication time

clock frequency and the area-time product

and also has certain advantages in the overall Optimal ate pair implementation.

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references

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Research on F p 2 -FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture

DOI：10.11959/j.issn.1000-436x.2022040

摘要

Abstract

关键词

Keywords

references

Research on $F_{p^{2}}$ -FIOSmodular multiplication algorithm for bilinear pairs and its implementation architecture