VLSI architecture design of motion compensation for MPEG-4

LIU Long; HAN Chong-zhao; WANG Zhan-hui

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VLSI architecture design of motion compensation for MPEG-4

更新时间：2024-10-14

- VLSI architecture design of motion compensation for MPEG-4
- Issue 11, (2005)
- 作者机构：
  
  1. 西安交通大学综合自动化研究所
  2. 海军工程大学信息与电气学院,陕西,西安,710049
  3. ,湖北,武汉,430033
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN919.81
- Published：2005
- 稿件说明：
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LIU Long, HAN Chong-zhao, WANG Zhan-hui. VLSI architecture design of motion compensation for MPEG-4[J]. 2005, (11).
DOI：

LIU Long, HAN Chong-zhao, WANG Zhan-hui. VLSI architecture design of motion compensation for MPEG-4[J]. 2005, (11). DOI：

摘要

针对MPEG-4解码中运动补偿控制复杂、数据吞吐量大、实现较困难

提出了一种适合MPEG-4的运动补偿硬件实现方案

解决了时序分配、输入输出控制等较难处理的问题。此方案已经在Xilinx ISE6.1i集成开发环境下

采用了VHDL进行描述

并使用了电子设计自动化(EDA)工具进行了模拟和验证。仿真和综合结果表明

设计的运动补偿处理器逻辑功能完全正确

而且可以满足MPEG-4 Core Profiles & Level2的实时编码要求

可用于MPEG-4的VLSI实现。

Abstract

In the light of complex control

high throughput and difficult implementation of motion compensation of MPEG-4 decoding

a motion compensation （MC） circuit solving the timing and I/O of decoding was presented for MPEG-4.The VLSI architecture and implementation in terms of VHDL were designed in the Xilinx ISE6.1 i environment and some simulations were carried out in tools of electronic design automation （EDA）. The experimental results show that the VLSI processor designed can perform correct logic functions and can achieve a real-time coding for MPEG-4 Core Profile and Level 2.

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