To solve the problem of inefficiency of implementing embedded block coding in JPEG 2000

a novel fast algo- rithm to achieve word-level sequential and parallel bit plane coding （BPC） was proposed. The proposed BPC algorithm adopted a technique of performing the coding pass prediction and context formation as parallel and pipelined fashion. By using this BPC algorithm

the coefficients bit modeling for all bit planes in a code block were completed as parallel and sequential mode by one scan. Based on this new coding algorithm

an efficient high-speed architecture （HSA） was pre- sented

which could perform context formation for 4 coefficients belonging to the same stripe column at one intra- clock cycle

and achieve context formation for an N×N code-block in approximate N 2/4 intra- clock cycles. Theoretical analy- sis and experimental results demonstrate that

the proposed HSA could significantly increase throughput rate with good performance in terms of speedup to cost

compared with the up-to-date design.