VLSI design of an irregular LDPC decoder in DTMB

CHEN Yun; ZENG Xiao-yang; LIN Yi-fan; XIANG Bo; DENG Yun-song

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VLSI design of an irregular LDPC decoder in DTMB

更新时间：2024-10-14

- VLSI design of an irregular LDPC decoder in DTMB
- Issue 8, Pages: 61-66(2007)
- 作者机构：
  
  1. 复旦大学专用集成电路与系统国家重点实验室
  2. 复旦大学专用集成电路与系统国家重点实验室,上海,201203
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN764
- Published：2007
- 稿件说明：
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CHEN Yun, ZENG Xiao-yang, LIN Yi-fan, et al. VLSI design of an irregular LDPC decoder in DTMB[J]. 2007, (8): 61-66.
DOI：

CHEN Yun, ZENG Xiao-yang, LIN Yi-fan, et al. VLSI design of an irregular LDPC decoder in DTMB[J]. 2007, (8): 61-66. DOI：

摘要

在完全符合数字电视地面传输中国国家标准(DTMB)的芯片系统中

实现了一个码长为7 493bit

同时支持3种码率(0.4

0.6

0.8)的非规则LDPC码解码器。在该设计中

使用了一种新的存储器调用的控制策略

在只比单码率最多增加不到5%的存储器的情况下

实现了3种码率存储器的复用。在最大迭代次数为15次的情况下

可以达到150Mbit/s的高吞吐率

而在DTMB中所需的50Mbit/s数据率要求下

迭代次数可高达45次。还给出了FPGA的综合报告和基于SMIC 0.13μm CMOS工艺下的解码器版图。

Abstract

An irregular LDPC decoder with a code length of 7 493 bits for DTMB system was implemented based on SMIC 0.13μm CMOS process.A new method to control memories was proposed

which can reuse memories for three different code rates only by increasing 5% memory usage.The throughput of the LDPC decoder is up to 150Mbit/s with the max iterative number of 15.While keeping the throughout of 50Mbit/s

its max iterative number can reach 45.The FPGA synthesis reports and the decoder layout in SMIC 0.13μm CMOS technology are given.

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