Design of low power and high speed FFT/IFFT processor for UWB system

LIU Liang; WANG Xue-jing; YE Fan; REN Jun-yan

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Design of low power and high speed FFT/IFFT processor for UWB system

更新时间：2024-10-14

- Design of low power and high speed FFT/IFFT processor for UWB system
- Issue 9, Pages: 40-45(2008)
- 作者机构：
  
  复旦大学专用集成电路与系统国家重点实验室微纳创新平台
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN492;TN914
- Published：2008
- 稿件说明：
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LIU Liang, WANG Xue-jing, YE Fan, et al. Design of low power and high speed FFT/IFFT processor for UWB system[J]. 2008, (9): 40-45.
DOI：

LIU Liang, WANG Xue-jing, YE Fan, et al. Design of low power and high speed FFT/IFFT processor for UWB system[J]. 2008, (9): 40-45. DOI：

摘要

设计了一种应用于超宽带(UWB)无线通信系统中的FFT/IFFT处理器。采用8×8×2混合基算法进行FFT运算

实现了2路64点或者1路128点FFT功能

并为该算法提出了一种新型的8路并行反馈结构。该结构提高了处理器的数据吞吐率

降低了芯片功耗。为了减少处理器中的乘法数目

提高时序性能

提出了改进型移位加算法。设计的FFT/IFFT处理器采用SMIC 0.13μm CMOS工艺制造

芯片的核心面积为1.44mm2。测试结果表明

该芯片最高数据吞吐率到达1Gsample/s

在典型的工作频率500Msample/s下

芯片功耗为39.6mW。与现有同类型FFT芯片相比

该芯片面积缩小了40%

功耗减少了45%。

Abstract

A new 128/64-point FFT/IFFT processor used in Ultra-Wide-Band（UWB） system was presented.The proces-sor

which is based on 8×8×2 mixed radix algorithm

can deal with multiple inputs more efficiently for MIMO applica-tions.A new eight-path-feedback structure

which can provide a higher throughput and lower power dissipation

was proposed.The test chip has been fabricated using SMIC 0.13μm single-poly and eight-metal CMOS process with a core area of 1.44mm2.The throughput of this chip is up to 1Gsample/s

and the power dissipation is 39.6mW when it works at the throughput of 500Msample/s which meets the UWB standard.This chip reduces 40% of core area and saves 45% of power dissipation compared with those existing 128-point FFT processors.

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