Design and implementation for partition dynamically vector quantization chip
|更新时间:2024-10-14
|
Design and implementation for partition dynamically vector quantization chip
Vol. 30, Issue 7, Pages: 91-98(2009)
作者机构:
西安理工大学电子工程系
作者简介:
基金信息:
DOI:
CLC:TN402
Published:2009
稿件说明:
移动端阅览
YU Ning-mei, WANG Dong-fang, LIAO Yu-min, et al. Design and implementation for partition dynamically vector quantization chip[J]. 2009, 30(7): 91-98.
DOI:
YU Ning-mei, WANG Dong-fang, LIAO Yu-min, et al. Design and implementation for partition dynamically vector quantization chip[J]. 2009, 30(7): 91-98.DOI:
Design and implementation for partition dynamically vector quantization chip
Partition dynamically vector quantization(PDVQ) chip was researched and produced to encode images.Before encoding
it first judged the correlation of the encoding image block
and then decided to choose the size of the image blocks.Test result shows that PDVQ chip can improve the compression rate to 27% in average by contrasting with the normal VQ
even to 64%.The size of the codebook in PDVQ chip was 256×16 byte
and all codevectors in the codebook were categorized by direction
in each category codebook codewords were sorted in the ascending order of their sum
this kind codebook architecture could reduce search range largely.The VLSI architecture of PDVQ chip was implemented based on Charter 0.35μm CMOS standard cell technology
its chip area was 2.08mm×2.08mm.Test result shows that
at 3.0V power supply
PDVQ chip can operate up to 100MHz.At this operation
its power dissipation is 295mW
and it can support real-time encoding application for 512×512 gray images at 30fame/s.