面向软件定义晶上系统的安全互连接口架构

李沛杰; 沈剑良; 郭威; 曹志鹏; 梅波

doi:10.11959/j.issn.1000-436x.2024190

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面向软件定义晶上系统的安全互连接口架构

学术论文 | 更新时间：2024-11-14

- 面向软件定义晶上系统的安全互连接口架构
- Secure interface architecture for the software defined system on wafer
- 通信学报 2024年45卷第10期页码：41-54
- 作者机构：
  
  信息工程大学信息技术研究所，河南郑州 450002
- 作者简介：
  
  [ "李沛杰（1990- ），男，山西襄汾人，信息工程大学助理研究员、博士生，主要研究方向为软件定义晶上系统、软件定义互连、硬件安全等。" ]
  [ "沈剑良（1982- ），男，浙江德清人，博士，信息工程大学研究员、博士生导师，主要研究方向为片上系统芯片、软件定义晶上系、可重构计算等。" ]
  [ "郭威（1990- ），男，北京人，博士，信息工程大学副研究员，主要研究方向为网络空间主动防御、计算机体系结构、人工智能与大数据、内生安全等。" ]
  [ "曹志鹏（1996- ），男，陕西西安人，信息工程大学博士生，主要研究方向为软件定义晶上系统、计算机体系结构、互连网络等。" ]
  [ "梅波（1998- ），男，安徽宣城人，信息工程大学博士生，主要研究方向为内生安全、硬件木马防御等。" ]
- 基金信息：
  
  国家重点研发计划基金资助项目(2022YFB4401401)
- DOI：10.11959/j.issn.1000-436x.2024190
  中图分类号： TP309.2
- 收稿：2024-07-23，
  
  修回：2024-09-28，
  
  纸质出版：2024-10-25
- 稿件说明：
移动端阅览
李沛杰,沈剑良,郭威等.面向软件定义晶上系统的安全互连接口架构[J].通信学报,2024,45(10):41-54.

LI Peijie,SHEN Jianliang,GUO Wei,et al.Secure interface architecture for the software defined system on wafer[J].Journal on Communications,2024,45(10):41-54.
李沛杰,沈剑良,郭威等.面向软件定义晶上系统的安全互连接口架构[J].通信学报,2024,45(10):41-54. DOI： 10.11959/j.issn.1000-436x.2024190.

LI Peijie,SHEN Jianliang,GUO Wei,et al.Secure interface architecture for the software defined system on wafer[J].Journal on Communications,2024,45(10):41-54. DOI： 10.11959/j.issn.1000-436x.2024190.

摘要

针对软件定义晶上系统中芯粒互连接口缺乏动态性和异构性导致系统易被恶意芯粒攻击的问题，通过最大限度复用功能逻辑，提出一种动态异构冗余的安全互连接口架构。首先基于软件定义互连技术在电路结构、传输协议和报文结构上进行异构性设计，然后增加裁决调度机制实现威胁定位和动态重构，最后对所提架构进行了晶圆级芯粒流片验证。实验表明，所设计的安全互连接口架构在有限资源开销下具有良好的威胁检测、定位与动态防御效果。

Abstract

To address the lack of dynamic and heterologous characteristics for interconnect interface in software defined system on wafer

a dynamic heterologous redundancy secure interface (DHR-SI) architecture was proposed to maximize the reuse of functional logic. First

based on software defined interconnect technology

the heterogeneous characteristics were implemented in terms of circuit structure

transmission protocol

and message content. And then an arbitration scheduling mechanism was designed to achieve threat localization and dynamic reconfiguration. Finally

the architecture was validated and tested through a wafer scale chiplet. The experimental analysis shows that the proposed DHR-SI architecture has excellent threat detection

localization

and dynamic defense capabilities with limited overhead.

关键词

Keywords

references

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