面向格密码的可配置基-4 NTT硬件优化与实现
Configurable radix-4 NTT hardware optimization and implementation for lattice-based cryptography
- 通信学报 2024年45卷第10期 页码：163-179
- 作者机构：
1.郑州大学计算机与人工智能学院，河南 郑州 450001
2.河南省网络密码技术重点实验室，河南 郑州 450001
- 作者简介：
[ "周清雷（1962- ），男，河南郑州人，博士，郑州大学教授，主要研究方向为信息安全、自动机理论和计算复杂性理论。" ]
[ "韩贺茹（1999- ），女，河南驻马店人，郑州大学硕士生，主要研究方向为后量子密码、高性能可重构计算。" ]
[ "李斌（1986- ），男，河南郑州人，博士，郑州大学讲师，主要研究方向为信息安全、可重构计算。" ]
[ "刘宇航（1999- ），男，河南商丘人，郑州大学硕士生，主要研究方向为隐私保护计算、可重构硬件架构设计。" ]
- 基金信息：河南省科技攻关基金资助项目(232102211055);河南省网络密码技术重点实验室研究课题基金资助项目(LNCT2022-A14);河南省重大科技专项基金资助项目(221100210600)
DOI：10.11959/j.issn.1000-436x.2024188
中图分类号： TP309收稿：2024-05-15，
修回：2024-10-08，
纸质出版：2024-10-25
- 稿件说明：
移动端阅览
周清雷,韩贺茹,李斌等.面向格密码的可配置基-4 NTT硬件优化与实现[J].通信学报,2024,45(10):163-179.
ZHOU Qinglei,HAN Heru,LI Bin,et al.Configurable radix-4 NTT hardware optimization and implementation for lattice-based cryptography[J].Journal on Communications,2024,45(10):163-179.
周清雷,韩贺茹,李斌等.面向格密码的可配置基-4 NTT硬件优化与实现[J].通信学报,2024,45(10):163-179. DOI： 10.11959/j.issn.1000-436x.2024188.
ZHOU Qinglei,HAN Heru,LI Bin,et al.Configurable radix-4 NTT hardware optimization and implementation for lattice-based cryptography[J].Journal on Communications,2024,45(10):163-179. DOI： 10.11959/j.issn.1000-436x.2024188.
摘要
针对数论变换（NTT）优化格密码算法中的多项式乘法问题，以及NTT设计趋向多应用场景的需求，提出了一种面向格密码的可配置基-4 NTT硬件结构。通过分析基-4 NTT/INTT（Inverse NTT）算法流程，设计了高效的现场可编程门阵列（FPGA）整体结构。该结构具备参数化的运行时可配置性和满足多样化需求的编译时可配置性，以流水线方式构建基-4 NTT统一化蝶形单元，并对模除、模约减等关键模块进行优化，提高了计算效率和可配置性。此外，提出可配置多RAM存储优化设计方案及数据存储分配算法，以避免内存冲突、提高数据访问效率。与相关方案的对比及分析表明，以Dilithium算法为例，所提方案不仅具有较高的工作频率，还实现了面积上高达54.3%的优化和吞吐量高达2倍的提升，能够充分发挥FPGA的计算优势。
Abstract
In response to the complex polynomial multiplication issue in lattice-based cryptography algorithms optimized with number theoretic transform (NTT)
as well as the demand for NTT designs catering to multiple application scenarios
a configurable radix-4 NTT hardware architecture for lattice-based cryptography was proposed. By analyzing the radix-4 NTT/INTT (inverse NTT) algorithm process
an efficient FPGA architecture was designed
which parameterized runtime configurability and offered compile-time configurability to meet diverse requirements
a pipeline approach was used to construct the radix-4 NTT unified butterfly unit
key algorithmic modules such as modular division and modular reduction were deeply optimized
thereby enhancing computational efficiency and reconfigurability. Additionally
a configurable multi-RAM storage optimization design scheme and data storage allocation algorithm were proposed to avoid memory conflicts and improve data access efficiency. Comparison and analysis with related approaches show that
using the Dilithium algorithm as an example
the proposed design not only achieves a high operational frequency but also achieves up to 54.3% improvement in area and 2 times optimization in throughput
fully leveraging the computational advantages of FPGA.
关键词
Keywords
references
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