可重构的素域SM2算法优化方法

李斌; 周清雷; 陈晓杰; 冯峰

doi:10.11959/j.issn.1000-436x.2022043

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可重构的素域SM2算法优化方法

学术论文 | 更新时间：2024-06-05

- 可重构的素域SM2算法优化方法
- Optimization of reconfigurable SM2 algorithm over prime filed
- 通信学报 2022年43卷第3期页码：30-41
- 作者机构：
  
  1. 郑州大学计算机与人工智能学院，河南郑州 450001
  2. 数学工程与先进计算国家重点实验室，河南郑州 450001
- 作者简介：
  
  [ "李斌（1986- ），男，河南郑州人，博士，郑州大学讲师，主要研究方向为信息安全、可重构计算" ]
  [ "周清雷（1962- ），男，河南新乡人，博士，郑州大学教授，主要研究方向为信息安全、自动机理论和计算复杂性理论" ]
  [ "陈晓杰（1993- ），男，河南武陟人，数学工程与先进计算国家重点实验室博士生，主要研究方向为信息安全、可重构计算" ]
  [ "冯峰（1990- ），男，河南新乡人，郑州大学博士生，主要研究方向为信息安全" ]
- 基金信息：
  
  国家重点研发计划基金资助项目(2016YFB0800100);国家重点研发计划基金资助项目(2016YFB0800101);国家自然科学基金资助项目(61572444)
- DOI：10.11959/j.issn.1000-436x.2022043
  中图分类号： TP309
- 网络出版日期：2022-03，
  
  纸质出版日期：2022-03-25
- 稿件说明：
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李斌, 周清雷, 陈晓杰, 等. 可重构的素域SM2算法优化方法[J]. 通信学报, 2022,43(3):30-41.

Bin LI, Qinglei ZHOU, Xiaojie CHEN, et al. Optimization of reconfigurable SM2 algorithm over prime filed[J]. Journal on communications, 2022, 43(3): 30-41.
李斌, 周清雷, 陈晓杰, 等. 可重构的素域SM2算法优化方法[J]. 通信学报, 2022,43(3):30-41. DOI： 10.11959/j.issn.1000-436x.2022043.

Bin LI, Qinglei ZHOU, Xiaojie CHEN, et al. Optimization of reconfigurable SM2 algorithm over prime filed[J]. Journal on communications, 2022, 43(3): 30-41. DOI： 10.11959/j.issn.1000-436x.2022043.

摘要

针对SM2算法软件效率低、硬件实现资源利用率低、可扩展性差的问题，提出了一种可重构的素域SM2算法优化方法。通过对SM2算法的深入分析，从不同计算阶段和计算特点着手，分别采用KOA快速乘法、快速模约减和Barrett算法实现推荐或任意参数的模乘运算，并优化改进基为4的扩展欧几里得算法加速模逆运算。然后，在标准射影坐标系下以蒙哥马利方法提高点乘运算效率，并优化了点加和倍点数据流，将运算周期缩短至12个时钟。同时，在FPGA内部实现了快速的坐标系转换。最后，设计实现了多SM2的并行调度管理，满足日益多样化的应用需求。实验结果分析表明，所优化的SM2充分利用了FPGA的资源，缩短了点乘周期，每秒计算次数最多较CPU（Intel i5-8300）高352.48倍，提高了计算性能和可扩展性。

Abstract

Aiming at the problems of inefficient of software

low utilization of hardware resources and poor scalability of SM2 algorithm

a reconfigurable optimization method of SM2 algorithm over prime filed was proposed.Through in-depth analysis of the SM2 algorithm

starting from different computation stages and characteristics

respectively using KOA fast multiplication

fast modular reduction and Barrett algorithm to achieve recommended or arbitrary parameters of the modular multiplication operation

and the radix-4 extended Euclidean algorithm was optimized and improved to accelerate the modular inverse operation.Then

in the standard projective coordinate system

the Montgomery method was used to improve the efficiency of point multiplication

and the data flow of point addition and double point was optimized to shorten the operation cycle to 12 clocks.At the same time

fast coordinate system conversion was realized inside the FPGA.Finally

the parallel scheduling management of multi-SM2 was designed and implemented to meet the computational requirements of multiple applications.The experimental results show that the optimized SM2 makes full use of FPGA resources and shortens the cycle of point multiplication.The maximum number of calculations per second is 352.48 times higher than the CPU (Intel i5-8300)

which improves the performance and scalability.

关键词

Keywords

references

JAVEED K , WANG X J . Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp [C ] // Proceedings of 2014 24th International Conference on Field Programmable Logic and Applications (FPL) . Piscataway:IEEE Press , 2014 : 1 - 6 .

AMIET D , CURIGER A , ZBINDEN P . Flexible FPGA-based architectures for curve point multiplication over GF(p) [C ] // Proceedings of 2016 Euromicro Conference on Digital System Design (DSD) . Piscataway:IEEE Press , 2016 : 107 - 114 .

FENG X , LI S G . A high-speed and SPA-resistant implementation of ECC point multiplication over GF(p) [C ] // Proceedings of 2017 IEEE Trustcom/BigDataSE/ICESS . Piscataway:IEEE Press , 2017 : 255 - 260 .

ZHAO Z W , BAI G Q . Ultra high-speed SM2 ASIC implementation [C ] // Proceedings of 2014 IEEE 13th International Conference on Trust,Security and Privacy in Computing and Communications . Piscataway:IEEE Press , 2014 : 182 - 188 .

ZHANG D , BAI G Q . Ultra high-performance ASIC implementation of SM2 with power-analysis resistance [C ] // Proceedings of 2015 IEEE International Conference on Electron Devices and Solid-State Circuits . Piscataway:IEEE Press , 2015 : 523 - 526 .

HOSSAIN M S , KONG Y N , SAEEDI E , et al . High-performance elliptic curve cryptography processor over NIST prime fields [J ] . IET Computers ＆ Digital Techniques , 2017 , 11 ( 1 ): 33 - 42 .

韩晓薇 , 乌力吉 , 王蓓蓓 , 等 . 抗简单功耗攻击的SM2原子算法 [J ] . 计算机研究与发展 , 2016 , 53 ( 8 ): 1850 - 1856 .

HAN X W , WU L J , WANG B B , et al . Atomic algorithm against simple power attack of SM2 [J ] . Journal of Computer Research and Development , 2016 , 53 ( 8 ): 1850 - 1856 .

JAVEED K , WANG X J . Low latency flexible FPGA implementation of point multiplication on elliptic curves over GF(p) [J ] . International Journal of Circuit Theory and Applications , 2017 , 45 ( 2 ): 214 - 228 .

RAHMAN M S , HOSSAIN M S , RAHAT E H , et al . Efficient hardware implementation of 256-bit ECC processor over prime field [C ] // Proceedings of 2019 International Conference on Electrical,Computer and Communication Engineering (ECCE) . Piscataway:IEEE Press , 2019 : 1 - 6 .

JÄRVINEN K , MIELE A , AZARDERAKHSH R , et al . FourQ on FPGA:new hardware speed records for elliptic curve cryptography over large prime characteristic fields [C ] // International Conference on Cryptographic Hardware and Embedded Systems . Berlin:Springer , 2016 : 517 - 537 .

LI W , LIU J H , BAI G Q . High-speed implementation of SM2 based on fast modulus inverse algorithm [C ] // Proceedings of 2018 China Semiconductor Technology International Conference (CSTIC) . Piscataway:IEEE Press , 2018 : 1 - 3 .

DING J N , LI S G . A reconfigurable high-speed ECC processor over NIST primes [C ] // Proceedings of 2017 IEEE Trustcom/ BigDataSE/ICESS . Piscataway:IEEE Press , 2017 : 1064 - 1069 .

YANG D Y , DAI Z B , LI W , et al . An efficient ASIC implementation of public key cryptography algorithm SM2 based on module arithmetic logic unit [C ] // Proceedings of 2019 IEEE 13th International Conference on ASIC . Piscataway:IEEE Press , 2019 : 1 - 4 .

HOSSAIN M R , HOSSAIN M S . Efficient FPGA implementation of modular arithmetic for elliptic curve cryptography [C ] // Proceedings of 2019 International Conference on Electrical,Computer and Communication Engineering (ECCE) . Piscataway:IEEE Press , 2019 : 1 - 6 .

DING J N , LI S G , GU Z . High-speed ECC processor over NIST prime fields applied with toom-cook multiplication [J ] . IEEE Transactions on Circuits and Systems I:Regular Papers , 2019 , 66 ( 3 ): 1003 - 1016 .

ROY D B , MUKHOPADHYAY D . High-speed implementation of ECC scalar multiplication in GF(p) for generic Montgomery curves [J ] . IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2019 , 27 ( 7 ): 1587 - 1600 .

ISLAM M M , HOSSAIN M S , HASAN M K , et al . FPGA implementation of high-speed area-efficient processor for elliptic curve point multiplication over prime field [J ] . IEEE Access , 2019 , 7 : 178811 - 178826 .

KHAN S , JAVEED K , SHAH Y A . High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications [J ] . Microprocessors and Microsystems , 2018 , 62 : 91 - 101 .

ZHANG D , BAI G Q . High-performance implementation of SM2 based on FPGA [C ] // Proceedings of 2016 8th IEEE International Conference on Communication Software and Networks . Piscataway:IEEE Press , 2016 : 718 - 722 .

GARG H K , XIAO H S . New residue arithmetic based barrett algorithms:modular integer computations [J ] . IEEE Access , 2016 , 4 : 4882 - 4890 .

BRIER E , JOYE M . Weierstraß elliptic curves and side-channel attacks [C ] // International Workshop on Public Key Cryptography . Berlin:Springer , 2002 : 335 - 345 .

JAVEED K , WANG X J . FPGA based high speed SPA resistant elliptic curve scalar multiplier architecture [J ] . International Journal of Reconfigurable Computing,2016 , 2016 :6371403.

YU W , WANG K P , LI B , et al . Montgomery algorithm over a prime field [J ] . Chinese Journal of Electronics , 2019 , 28 ( 1 ): 39 - 44 .

HU X H , ZHENG X , ZHANG S S , et al . A high-performance elliptic curve cryptographic processor of SM2 over GF(p) [J ] . Electronics , 2019 , 8 ( 4 ): 431 .

WU T , YE J H , LU J . Hardware implementation of SM2 ECC protocols on FPGAs [C ] // Proceedings of 2021 IEEE 5th Information Technology,Networking,Electronic and Automation Control Conference . Piscataway:IEEE Press , 2021 : 33 - 37 .

王腾飞 , 张海峰 , 许森 . SM2 专用指令协处理器设计与实现 [J ] . 计算机工程与应用 , 2022 , 58 ( 2 ): 102 - 109 .

WANG T F , ZHANG H F , XU S . Design and implementation of SM2 co-processor with specific instructions [J ] . Computer Engineering and Applications , 2022 , 58 ( 2 ): 102 - 109 .

XIAO Y , LIN W B , ZHAO Y , et al . A high-speed elliptic curve cryptography processor for teleoperated systems security [J ] . Mathematical Problems in Engineering,2021 , 2021 :6633925.

杨国强 , 丁杭超 , 邹静 , 等 . 基于高性能密码实现的大数据安全方案 [J ] . 计算机研究与发展 , 2019 , 56 ( 10 ): 2207 - 2215 .

YANG G Q , DING H C , ZOU J , et al . A big data security scheme based on high-performance cryptography implementation [J ] . Journal of Computer Research and Development , 2019 , 56 ( 10 ): 2207 - 2215 .

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