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1. 哈尔滨理工大学计算机科学与技术学院,黑龙江 哈尔滨 150080
2. 哈尔滨理工大学电气与电子工程学院,黑龙江 哈尔滨 150080
3. 黑龙江省网络空间研究中心,黑龙江 哈尔滨 150090
[ "姜占鹏(1984-),男,黑龙江哈尔滨人,博士,哈尔滨理工大学副教授,主要研究方向为嵌入式微处理器和总线接口电路设计等" ]
[ "孙铭玮(1995-),男,黑龙江密山人,哈尔滨理工大学硕士生,主要研究方向为数字集成电路设计" ]
[ "黄海(1982-),男,内蒙古巴彦淖尔人,博士,哈尔滨理工大学教授、博士生导师,主要研究方向为信息安全、可重构技术、集成电路设计等" ]
[ "徐江(1997-),男,山东日照人,哈尔滨理工大学硕士生,主要研究方向为信息安全" ]
[ "刘志伟(1987-),男,黑龙江哈尔滨人,博士,哈尔滨理工大学讲师,主要研究方向为可重构计算、高速密码算法、并行加密技术、密码芯片的安全设计等" ]
[ "白瑞(1990-),男,内蒙古海拉尔人,黑龙江省网络空间研究中心工程师,主要研究方向为网络安全、卫星应用、大数据等" ]
[ "方舟(1983-),女,黑龙江哈尔滨人,博士,黑龙江省网络空间研究中心高级工程师,主要研究方向为物联网内容安全与隐私保护、网络安全、卫星应用、大数据等" ]
[ "曲家兴(1979-),男,黑龙江哈尔滨人,博士,黑龙江省网络空间研究中心研究员级高级工程师,主要研究方向为物联网内容安全与隐私保护、网络安全、卫星应用、大数据等" ]
网络出版日期:2022-02,
纸质出版日期:2022-02-25
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姜占鹏, 孙铭玮, 黄海, 等. 面向双线性对的
Zhanpeng JIANG, Mingwei SUN, Hai HUANG, et al. Research on
姜占鹏, 孙铭玮, 黄海, 等. 面向双线性对的
Zhanpeng JIANG, Mingwei SUN, Hai HUANG, et al. Research on
针对双线性对运算效率低的问题,提出了一种面向双线性对的二次扩域细集成操作数扫描(
<math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub> </math>
-FIOS)模乘算法。该算法通过优化二次扩域下(AB+CD)mod P的运算过程,有效降低了模乘中的模约减次数;设计了满足不同应用需求的2种硬件架构及其调度方式以提升算法的计算效率;采用TSMC 55 nm工艺实现了双线性对运算单元。与现有文献相比,所设计的架构在一次模乘时间、时钟频率和面积时间积等性能指标上优于同类模乘设计,在整体Optimal ate对运算实现上也有一定的优势。
A quadratic extended-domain finely integrated operand scanning (
<math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub> </math>
-FIOS) modular multiplication algorithm for bilinear pairs was proposed to address the problem of low efficiency of bilinear pair operations.The algorithm effectively reduced the number of modular reductions in modular multiplication by optimizing the operation process of (AB+CD)mod P under the quadratic expansion domain.Two hardware architectures and their scheduling methods were designed to meet different application requirements.In order to improve the computational efficiency of the algorithm
the TSMC 55 nm process was used to realize the bilinear pairing operation unit.Compared with the existing literature
the designed architecture is superior to similar modular multiplication designs in performance indicators such as the first modular multiplication time
clock frequency and the area-time product
and also has certain advantages in the overall Optimal ate pair implementation.
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