In the light of complex control

high throughput and difficult implementation of motion compensation of MPEG-4 decoding

a motion compensation （MC） circuit solving the timing and I/O of decoding was presented for MPEG-4.The VLSI architecture and implementation in terms of VHDL were designed in the Xilinx ISE6.1 i environment and some simulations were carried out in tools of electronic design automation （EDA）. The experimental results show that the VLSI processor designed can perform correct logic functions and can achieve a real-time coding for MPEG-4 Core Profile and Level 2.