您当前的位置:
首页 >
文章列表页 >
Design and FPGA implementation of an efficient LDPC decodingsystem for the 5G-NR standard
更新时间:2026-09-16
    • Design and FPGA implementation of an efficient LDPC decodingsystem for the 5G-NR standard

    • Journal on Communications   (2026)
    • DOI:10.11959/j.issn.1000-436x.TXXB260342    

      CLC: TN911.22
    • Received:11 June 2026

      Revised:2026-09-12

      Accepted:14 September 2026

    移动端阅览

  • Sun Yuan, Yi Yang, Gong Fengkui, et al. Design and FPGA implementation of an efficient LDPC decodingsystem for the 5G-NR standard[J/OL]. Journal on Communications, 2026. DOI: 10.11959/j.issn.1000-436x.TXXB260342.

  •  
  •  

0

Views

0

下载量

0

CSCD

Alert me when the article has been cited
提交
Tools
Download
Export Citation
Share
Add to favorites
Add to my album

Related Articles

Low-complexity likelihood probability derivation algorithm for non-binary LDPC-coded modulation system
Efficient storage method for FPGA-based partially parallel QC-LDPC decoder
Design of a fused homomorphic LayerNorm scheme based on CKKS functional Bootstrapping
Advances in cross-medium magnetic induction communication: theories, technologies, and applications
Low T-depth quantum circuit implementation of SM3 hash function

Related Author

Guang-hua HE
Bao-ming BAI
Xiao MA
Bing LI
Rui-jia YUAN
Bao-ming BAI

Related Institution

State Key Lab of Integrated Service Networks,Xidian University
School of Information Science and Technology,Sun Yat-sen University
Science and Technology on Space Microwave Laborator
State Key Lab of Integrated Services Networks,Xidian University
Science and Technology on Information Transmission and Dissemination in Communication Networks Lab,CETC No.54 Research Institute
0