Design of a RISC-V Cryptographic Coprocessorfor the SM2 and SM3 Algorithms

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更新时间：2026-07-01

- Design of a RISC-V Cryptographic Coprocessorfor the SM2 and SM3 Algorithms
- Journal on Communications (2026)
- 作者机构：
  
  北京电子科技学院电子与通信工程系，北京 100070
- 作者简介：
- 基金信息：
  
  Beijing Natural Science Foundation(L251067);Science and Technology Project of the National Archives Administration of China(2025-Z-009);Fundamental Research Funds for the Central Universities(3282025045)
- DOI：10.11959/j.issn.1000-436x.TXXB260187
  CLC： TP332;TP309
- Received：08 April 2026，
  
  Revised：2026-06-27，
  
  Accepted：01 July 2026，
- 稿件说明：
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Li Xiuying, E Jiayan, Wu Xiuyun, et al. Design of a RISC-V Cryptographic Coprocessorfor the SM2 and SM3 Algorithms[J/OL]. Journal on Communications, 2026.
DOI：

Li Xiuying, E Jiayan, Wu Xiuyun, et al. Design of a RISC-V Cryptographic Coprocessorfor the SM2 and SM3 Algorithms[J/OL]. Journal on Communications, 2026. DOI： 10.11959/j.issn.1000-436x.TXXB260187.

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